1. Field of the Invention
The present invention relates to high density memory devices based on phase change based memory materials, including chalcogenide based materials and on other programmable resistive materials, and methods for refreshing such devices.
2. Description of Related Art
Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between amorphous and crystalline states by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher electrical resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile circuits, which can be read and written with random access.
The change from the amorphous to the crystalline state, referred to as set herein, is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change material to stabilize in the amorphous state.
It has been observed that some phase change memory cells in the reset state experience a decrease in resistance over time to below a threshold value used to distinguish between the reset and set states, resulting in data retention problems and bit errors for those memory cells. For example, a memory cell in which the active region has been reset to a generally amorphous state may over time develop a distribution of crystalline regions in the active region. If these crystalline regions connect to form a low resistance path through the active region, when the memory cell is read a lower resistance state will be detected and result in a data error. See, Gleixner, “Phase Change Memory Reliability”, 22nd NVSMW, 2007.
One attempt at addressing the data retention problems caused by the decrease in resistance over time is to maintain a relatively large read margin between the set and reset states. However, a relatively large read margin typically requires a slow set operation and a high reset current in order to obtain the large difference in resistance between the set and reset states. The relatively slow set operation and high reset current limit the operational speed of the device, restricting the use of phase change based memory circuits as high speed memory.
Thus, integrated circuits employing phase change based memory circuits typically also include other types of memory circuits in order to fulfill the memory performance requirements for the various functions of the integrated circuit. These different types of memory circuits are embedded at various locations in the integrated circuit, and typically include SRAM and DRAM memory circuits in order to provide high access speed memory for the integrated circuit. However, integration of different types of memory circuits for the various memory applications in an integrated circuit can be difficult and result in highly complex designs.
It has also been proposed to address the data retention problems by periodically refreshing phase change memory cells to offset any change in resistance that may occur over time.
One approach is to periodically read the resistance of each memory cell in the array to determine when to selectively perform a refresh operation on that particular memory cell. See, U.S. Patent Application Publication No. US 2008/0117704 entitled “Resistive Memory Including Selective Refresh Operation” by Happ et al., and U.S. Pat. No. 6,768,665 entitled “Refreshing Memory Cells of a Phase Change Material Memory Device” by Parkinson et al.
Another approach is to perform a refresh operation when the phase change memory has been accessed a number of times larger than a predetermined number. See, U.S. Patent Application Publication No. US 2008/0170431 entitled “Driving Method and System for a Phase Change Memory” by Sheu et al.
Another approach is to apply stress to a dummy set of memory cells based on the number of read and write operations performed on a main array of memory cells, and detecting changes in the resistance of the dummy set to determine when to refresh the main array of memory cells. See, U.S. Patent Application No. 2006/0158948 entitled “Memory Device” by Fuji.
It is therefore desirable to provide phase change based memory devices and methods for operating such devices which address the data retention issues discussed above and result in improved data storage performance.